搜索资源列表
uart
- 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
15Altera_IP
- 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
pro104_uart
- uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
rxd
- VHDL语言写的UART通信接收端程序，适用于RS232协议-VHDL language the receiving end of the UART communication procedures, applicable to RS232 protocol
uartfifo
- FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
uart_zhiwen
- RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
first_cpu
- nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
uart16750_latest.tar
- Implements a 16550/16750 UART core
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
CameraDriver
- This module use OV7620 digital camera on the 24-bit RBG (8:8:8) data and display that in RS232 uart interface
EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
traffic_light
- 交通灯控制系统，包括UART模块的设计和实现-Traffic light control system, including the UART module design and implementation of
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
vhdlshili
- 多个vhdl 实例，USB UART I2C VGA-vhdl USB UART I2C VGA
uart_module
- 实现精简的uart串口,格式起始位+8bit数据位+可配置的奇偶校验位+停止位-implement a smart UART interface
42cb47db-de04-443e-ac41-d950bce5756a
- vhdl uart代码，自己调试用的，大家指点，支持一下-vhdl uart
miniuart.tar
- 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL descr iption with a simple UART interface
Receiver
- This file recieves the serial data from the UART and forward to Serial To Parallel module
EXampleofFPGA
- FPGA的实验源程序，包括USB、UART、combus、I2c等，很适合学习使用-The use of FPGA tutorials, including USB, UART, combus, I2c and so on, very suitable for learning to use
uart_serial
- UART IP core in VHDL